Optimization and placement are driven by wire delay and actual availability of resources, rather than by measuring distance alone. Graph-based physical synthesis creates a detailed routing resource graph of pre-existing wires, switches and placement sites used for routing an FPGA. We believe our new graph-based physical synthesis technology delivers the accuracy needed to reduce design iterations and meet aggressive performance goals quickly and reliably.вЂќ вЂњBetter timing closure and physical optimizations all hinge on highly accurate timing estimations before running place and route. вЂњSynplicity was the first to deliver physical synthesis for FPGAs, and with our next-generation graph-based approach to physical synthesis, Synplicity continues its commitment to technology innovation,вЂќ said Andy Haines, senior vice president of marketing at Synplicity. The graph-based approach enables designers to close on aggressive timing requirements much faster while achieving a performance improvement of up to 20 percent compared with logic synthesis alone. The backbone of the Premier offering is Synplicity's new graph-based physical synthesis technology, an automated single-pass design flow that Synplicity claims delivers superior timing performance, dramatically improved timing correlation, and reduced design cycle time and iterations. Synplicity's Synplify Premier, just unveiled, offers an integrated environment featuring FPGA synthesis technology, an FPGA push button physical synthesis flow using graph-based physical synthesis and RTL Debugger.

SynplicityвЂ™s synplify pro